|
YS
Nobel Prize Winner
    
USA
1132 Posts |
Posted - Dec 14 2003 : 8:02:06 PM
|
Mike, you described your schematic pretty well. Actually you already had designed it. Connect power to resistor, resistor to pot, pot to cap, cap to ground. You need extra resistor to limit the minimum value of the pot. The Pot/Cap connection point could be connected to SCR gate directly but it is better to have some sort of triggering device. As you have 12V power, you can try CMOS gate with Shmitt trigger. There is a chip with 6 Smitt trigger inverters. Choose CMOS series which can handle 12V. connect inverter input to RC, and inverter output to other five inputs; other five outputs connect via 300 Ohm (or about that) resistor to SCR gate. So, you will have 5 inverters in parallel, which is allowed if they are on the same chip. As for delay, calculate approx. time value as T = RC.
|
 |
|